1. Field
Embodiments of the present invention generally relate to methods for fabricating dual material gate structures suitable for semiconductor devices. More specifically, embodiments of the invention relate to methods of fabricating gate structures having different gate electrode materials in different regions of semiconductor devices.
2. Description of the Related Art
Integrated circuits have evolved into complex devices that can include millions of components (e.g., transistors, capacitors and resistors) on a single chip. The evolution of chip designs continually requires faster circuitry and greater circuit density. The demands for greater circuit density necessitate a reduction in the dimensions of the integrated circuit components.
Generally, different transistors formed in different regions of an integrated circuit may require different electrical performance. For example, during fabricating a metal oxide semiconductor (MOS) transistor device, such as a complementary metal oxide semiconductor (CMOS), it is often desired to increase electron mobility and gate activation in n-type MOS device (NMOS) channels but to increase positive charged holes mobility and dopant activation in p-type MOS (PMOS) channels. In contrast, reduction of gate depletion effect of carriers is desired in both NMOS and PMOS region of the devices for minimum parasitic resistance and larger threshold voltage. Accordingly, different electrical performance, threshold voltage and work function requirements in n-type and p-type regions of a device presents a significant fabrication challenge.
FIGS. 1A-1C depict one embodiment of a device fabricated by a conventional fabrication process having n-type and p-type gate structure made from a similar material. FIG. 1A depicts a top view of a device structure having an n-type region 102 and a p-type region 104 formed on a substrate 108. In one embodiment, the n-type region 102 may have n-type field effect transistor (NFET) formed therein while the p-type region 104 may have p-type field effect transistor (PFET) formed therein. The n-type region 102 and p-type region 104 are aligned side by side within the device. Source 112 and drain 114 regions are formed in the substrate 108 underneath gate structures 160. The gate structure 160 includes a gate electrode layer 106 disposed on a gate dielectric layer 116. A dielectric layer 118, such as an interlayer dielectric layer (IDL), is disposed on the substrate 108 circumscribing the gate structure 160.
FIG. 1B depicts a cross sectional view of the gate structure 160 taken along the section line A-A′. The gate electrode layer 106 is disposed on the gate dielectric layer 116 on the substrate 108. Shallow trench isolations (STI) 120 fabricated from oxide materials is formed to isolate each n-type region and p-type region transistors formed on the gate structure 160.
FIG. 1C depicts another cross sectional view of the substrate 108 taken along the section line B-B′. The gate electrode layer 106 and the gate dielectric layer 116 are patterned to a predetermined critical dimension at a predetermined location on the substrate 108 between the source region 112 and drain region 114. The ILD layer 118 is deposited in between each gate structure 160, e.g., the gate electrode layer 106 and gate dielectric layer 116, formed on the substrate 108.
As the gate electrode layer 106 formed on the substrate 108 is utilized for both the n-type region 102 and the p-type region 104 devices, the electrical properties of the devices formed in the n-type region 102 and p-type region 104 are limited to the specific electrical performance properties for material selected for the gate electrode layer 106. The limitation of the material properties selected for fabricating the gate electrode 106 may only provide a specific work function in a certain range, thereby limiting the ability to meet different device requirements for both the n-type region 102 and the p-type region 104 of the substrate.
Therefore, there is a need for a method for fabricating a transistor having different electric performance at different regions.